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Espressif Systems /ESP32-H2 /SPI0 /SPI_MEM_PMS_REJECT

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Interpret as SPI_MEM_PMS_REJECT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SPI_MEM_REJECT_ADDR0 (SPI_MEM_PM_EN)SPI_MEM_PM_EN 0 (SPI_MEM_PMS_LD)SPI_MEM_PMS_LD 0 (SPI_MEM_PMS_ST)SPI_MEM_PMS_ST 0 (SPI_MEM_PMS_MULTI_HIT)SPI_MEM_PMS_MULTI_HIT 0 (SPI_MEM_PMS_IVD)SPI_MEM_PMS_IVD

Description

SPI1 access reject register

Fields

SPI_MEM_REJECT_ADDR

This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set.
SPI_MEM_PM_EN

Set this bit to enable SPI0/1 transfer permission control function.
SPI_MEM_PMS_LD

1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set.
SPI_MEM_PMS_ST

1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set.
SPI_MEM_PMS_MULTI_HIT

1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set.
SPI_MEM_PMS_IVD

1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data